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SmartScope Maker Kit

Use the SmartScope as an FPGA development platform with this special kit, which contains a preconfigured Smartscope, two programmers and the necessary cables.

Price $341.00

Member price $307.00

In Stock

This item expected shipping time is 5 days.


Use the SmartScope as an FPGA development platform with this special Maker kit. This Kit contains a special version of the SmartScope. In this version all internal headers have been assembled, exposing more FPGA pins which provide both read and write access. These headers are matched to a 0.1” grid, allowing you to align your breadboards with ease. Another header provides access to both analog inputs, so the SmartScope can digitize any voltages from your breadboard without the need of using patch wires.

Furthermore, the Maker Kit comes with a JTAG programmer, allowing you to hook straight into the FPGA. The JTAG programmer can be used to flash the FPGA and to use Xilinx’ ChipScope tool. The JTAG programmer can also be used on other Xilinx chips and dev boards.

Additionally, the Maker Kit comes with a PICKIT3 programmer for the USB controller, allowing you to experiment with the on-board USB controller as well.

Contents of the SmartScope Maker Kit:
• SmartScope, preconfigured version with preassembled headers on the board
• JTAG programmer for programming the FPGA in the SmartScope
• PICKIT 3 programmer for programming the USB controller in the SmartScope
• 2 Analog probes
• Digital probe cable with separate test clips
• 2 Mini USB connection cables
• USB A to USB B connection cable
• Connection cables for both programmers

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SKU 17942
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  1. It's a good price for the kit and what you get. The Hardware design is not totally open source however. The analog front end design is not included in the schematics, so If you want to mess with that you will have to copy their driver (and hope that it is correctly documented). They admit that the schematic has some issues as it is and all is not included. But if you can live with that, then it seems like a decent deal. I did not look at the VHDL code to see how well documented that is - the article seems to imply that it is OK,

    (Posted on 11/30/2016) - Review by LostInSpace

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