Xilinx announced a single-FPGA solution for telecommunications equipment manufacturers developing 40- and 100-Gigabit Ethernet (GE) solutions. Xilinx has added the Virtex-5 TXT platform to its family of 65-nanometer FPGAs. The platform consists of two devices that deliver 6.5Gbps serial transceivers, and are fully supported with application-specific IP, development tools, and reference designs for implementing high-bandwidth protocol bridging.
With its 48 6.5Gbps GTX transceivers, the Virtex-5 TXT platform is optimized for 100GE applications. It is designed to improve signal integrity for reliable operation of 10/100Gbps links, lower power consumption per channel for better reliability, and provide programmable support for multiple protocols, thus easily adapted to evolving standards for the interface between 100Gbps optical modules and the media access controller (MAC). Virtex-5 TXT devices offer a single-chip solution with built-in flexibility and re-programmability to scale as 40GE and 100GE hardware requirements and standards mature, while delivering the 600Gbps total bandwidth required today to build network bridges such as:
100GbE to 120Gbps Interlaken
40Gbps Quad XAUI to 50Gbps Interlaken
OC-768 to OTU-3
SFI-5 to 4xSFI4.2
Customers can begin designing with Virtex-5 TXT FPGA devices using the ISE design suite service pack 3 available online. The HSEC IP core is available from Sarance Technologies. The Virtex-5 TX150T and Virtex-5 TX240T devices will begin sampling by the end of calendar 2008 with production devices available in the first quarter of 2009.
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