IBM’s new z196 microprocessor integrates four cores with 1.4 billion transistors fabricated in 45-nm technology on an area of 512 square millimetres. Operating at 5.2 GHz, the processor features a superscalar CISC architecture with an out-of-order pipeline.
Each of the four cores has a dedicated 64-KB L1 instruction cache and 128-KB L1 data cache, as well as a 1.5-MB L2 cache. The chip also integrates a shared 24-MB L3 cache in eDRAM technology. Each processor core consists of six RISC-type execution units, two of which handle integer processing, along with two load/store units, a binary floating point processor, and an explicit decimal floating point processor.
The z196 processor is designed to support symmetrical multiprocessing (SMP), and several processors are combined in a multi-chip module (MCM) with extremely high processing power. This module also includes two storage controller (SC) units with an additional 192 MB of off-die L4 cache, which support data rates up to 48 GB/s. The SC chip has 1.5 billion transistors and nearly the same area as the z195 chip.
Each MCM contains six z195 processors and two SCs with a total cache size of 376.5 MB (L1–L4), and up to four MCMs can be fitted in a mainframe computer. The maximum configuration has a net processing capacity of 50 billion instructions per second and comprises 92 cores, of which 80 are available for application software and 12 are reserved for system administration and redundancy.
In case you’re thinking of building your own DIY PC with an MCM, you should be warned that the power consumption of the MCM is a tidy 1.8 kW.
Image: IBM
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