The JTAG Interface

The testing of large logic ICs such as FPGAs, CPLDs, ASICs, etc. is very difficult and time consuming when conventional test probes are used. The measurement of internal signals that are not brought out to an IC pin is impossible in this way. A number of companies have therefore joined forces to find a common solution to these problems. The result of this is the JTAG interface (IEEE 1149.1).In the industry (and also increasingly in the electronics hobby world) more and more use is made of larger, complex ICs. The advantages of these ICs are clear: the PCB can be smaller, the current consumption is less, parts of the design can be easily re-used, etc. Unfortunately this development also has a few disadvantages. The testing of these ICs hasn’t become any easier. In the case of SMD ICs the test probe has to be applied precisely in order to measure the signal at a specific pin and for BGA (ball grid array) ICs on a multi-layer PCB this becomes all but impossible.